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Katherine Yelick
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11	Performance Portable Optimizations for Loops Containing Communication Operations Costin Iancu Wei Chen, Katherine Yelick Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-10-24 14:33:15 Compiler optimizations Loop optimization Automatic parallelization Loop nest optimization CPU cache Program optimization Software pipelining Lookup table Distributed computing Fortran Compiler Algorithm
12	Optimization of Sparse Matrix-Vector Multiplication on Emerging Multicore Platforms Samuel Williams∗†, Leonid Oliker∗, Richard Vuduc§, John Shalf∗, Katherine Yelick∗†, James Demmel† ∗ CRD/NERSC, Lawrenc Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-09-07 00:12:17 Computer memory Cache Computer architecture Compiler optimizations CPU cache Central processing unit Opteron Cell Sparse matrix-vector multiplication Loop nest optimization Multi-core processor Advanced Micro Devices
13	Resource-Efficient, Hierarchical Auto-Tuning of a Hybrid Lattice Boltzmann Computation on the Cray XT4 Samuel Williams? , Jonathan Carter? , Leonid Oliker? John Shalf? , Katherine Yelick?† ? CRD/NERSC, Lawrence Berkele Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-09-06 23:52:12 Parallel computing Thread Multithreading Multi-core processor Task parallelism SPMD CPU cache Cell Message Passing Interface Algorithmic skeleton
14	Grey Ballard http://www.sandia.gov/~gmballa Sandia National Laboratories • PO Box 969, MS 9159 • Livermore, CA 94550 • (Education Add to Reading List Source URL: www.sandia.gov Language: English - Date: 2015-11-16 15:37:06 James Demmel Symposium on Parallelism in Algorithms and Architectures Numerical linear algebra Katherine Yelick Matrix multiplication International Parallel and Distributed Processing Symposium Jack Dongarra Parallel computing
15	OPTIMIZATION AND PERFORMANCE MODELING OF STENCIL COMPUTATIONS ON MODERN MICROPROCESSORS‡ KAUSHIK DATTA†, SHOAIB KAMIL∗†, SAMUEL WILLIAMS∗†, LEONID OLIKER∗, JOHN SHALF∗, KATHERINE YELICK∗† Abstract. St Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-09-06 23:58:43 Computer architecture Cache Central processing unit Microprocessors Computer memory CPU cache Stencil code Loop nest optimization Opteron POWER5 Cell Multi-core processor
16	DEGAS: Dynamic Global Address Space programming environments Katherine Yelick, Principal Investigator1 Lawrence Berkeley National Laboratory, Berkeley, California Vivek Sarkar, Co-Principal Investigator2 Rice University, Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2016-04-02 22:06:19 Parallel computing Partitioned global address space Coarray Fortran Unified Parallel C X10 Parallel programming model Multi-core processor PGAS Matrix multiplication algorithm Fortran Distributed computing OpenMP
17	A preliminary evaluation of the hardware acceleration of the Cray Gemini Interconnect for PGAS languages and comparison with MPI Hongzhang Shan, Nicholas J. Wright, John Shalf and Katherine Yelick CRD and NERSC Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-12-13 17:18:30 Parallel computing Message Passing Interface Partitioned global address space MPICH Coarray Fortran Cray Multi-core processor Blue Gene MVAPICH MPI K computer Parallel Virtual Machine
18	Opportunities and Challenges for Next Generation Computing Gregory D. Hager, Mark D. Hill, and Katherine Yelick Oct. 19, 2015 Version 1 Computing has dramatically changed nearly every aspect of our lives, from business a Add to Reading List Source URL: cra.org Language: English - Date: 2016-03-07 11:52:41 Parallel computing Concurrent computing Emerging technologies Classes of computers Distributed computing architecture Supercomputer Quantum computing Computing Computational science Simulation Cloud computing AI accelerator
19	Hierarchical Computation in the SPMD Programming Model Amir Kamil Katherine Yelick Add to Reading List Source URL: titanium.cs.berkeley.edu Language: English - Date: 2014-04-29 05:38:23 Parallel computing Computing Computer programming Software engineering SPMD Thread Task parallelism Data parallelism Barrier Synchronization Thread block Message Passing Interface